The Minimal Circuitry for FitzHugh-Nagumo neuron model with a Low Power Consumption and Optical I/O Interface
Alexey O. Manturov 1
Olga V. Drogaitseva 2
1Russian Presidential Academy of National Economy and Public Administration
2Saratov State Technical University
Abstract
The FitzHugh-Nagumo (FHN) model for biological neurons is one of the basic ones in modern neurosciences. The FHN model currently has more than several dozen known implementations in the form of electronic circuits and is extremely popular due to the simplicity of its formal description (a system of two first-order differential equations) and a relatively small number of control parameters.
At the same time, the FHN model allows us to demonstrate almost all the basic phenomena observed in biological neurons - spiking, bursting and possible complex behavior under the external force. Known experimental radio engineering implementations of the FHN model use either a discrete digital approach (e.g. FPGAs for quick numerical solving the FHN model equations and ADC-DAC for I/O analog data interfacing), or are based on the use of analog multipliers and operational amplifiers to implement the structure of the right-hand sides of the FHN model equations as it is well known from the old experience of using analog computers. Finally, we can separately pointed the software approach associated with modeling circuit implementations of FHN models, for example, in software simulators based on SPICE. In general, all the noted approaches are based on complex solutions, which practically limits the possibility of constructing more complex structures, for example, fully connected neural networks. Thus, the development of circuit implementations of the FHN model with a minimum number of active components remains actual.
In this work, a method for hardware implementation of the FHN model, based on discrete components - NMOS and BJT transistors without the use of discrete analog or digital LSI or VLSI components, is proposed. The possibility of design an optical interface that allows the implementation of arbitrary input/output connectivity is considered. The proposed circuit solutions can be implemented integrally by using, for example, 180 nm CMOS process technology.
Speaker
Alexey O. Manturov
Russian Presidential Academy of National Economy and Public Administration
Russia
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